A plasma reactor for processing a semiconductor wafer typically holds the wafer inside the reactor chamber using an electrostatic chuck (ESC). Plasma ion energy at the wafer surface is controlled by applying a bias voltage to the wafer through the ESC. The ESC essentially consists of an insulator layer having a top surface for supporting the wafer. An electrode or conductive mesh inside the insulator layer beneath the wafer receives a D.C. voltage, creating a voltage drop across the insulator layer between the electrode and the wafer, which produces an electrostatic force clamping the wafer to the ESC. The clamping force is determined by the difference between the time-average of the wafer voltage and the D.C. voltage applied to the ESC electrode. The clamping voltage must be accurately controlled (by accurately controlling the D.C. supply voltage) in order to avoid an insufficient clamping voltage or an excessive clamping voltage. An insufficient clamping voltage would allow the wafer to pop off of the ESC. An excessive clamping voltage would increase the current through the wafer to a level that risks damaging the circuit features formed on the wafer surface. (Current flows from the ESC electrode through the dielectric layer to the wafer and returns through the plasma in the chamber. The stronger the clamping force, the greater the conductivity between the wafer and the ESC, and therefore the greater the current through the wafer.) In order to accurately control the clamping voltage, the wafer D.C. voltage must be measured accurately. An error in wafer voltage measurement may lead to wafer pop off or to excessive ESC-wafer current.
Use of ESC-wafer contact to control the wafer temperature imposes even more stringent requirements for accurate control of clamping voltage. As disclosed in co-pending U.S. patent application Ser. No. 10/929,104, filed Aug. 26, 2004 entitled, “Gasless High Voltage High Contact Force Wafer Contact-Cooling Electrostatic Chuck,” by Douglas Buchberger, Jr. et al., and assigned to the present assignee, the ESC may be heated or cooled so that the wafer is either heated or cooled at a rate determined by the ESC clamping force. The wafer temperature may therefore be accurately set and controlled as desired. In fact, the heat transfer rate is so great as the clamping voltage is increased, that the wafer temperature may be maintained under much higher heat load than was formerly possible. Thus, for example, the wafer bias power may be increased beyond previously permitted levels. However, the wafer temperature range is limited because the clamping voltage cannot closely approach the upper limit (above which the wafer current is excessive) or the lower limit (below which the wafer may pop off the ESC), without more accurate determination of wafer voltage. (The clamping voltage is determined from the difference between the time average of the wafer voltage and the D.C. supply voltage.) Current methods for estimating wafer voltage tend to be inaccurate, so that the clamping voltage range must be limited to ensure that wafer voltage measurement errors do not cause the clamping voltage to violate the upper and lower limits.
An accurate method for determining wafer voltage is disclosed in co-pending U.S. patent application Ser. No. 10/440,364, filed May 16, 2003 by Daniel Hoffman and assigned to the present assignee. This method is applicable to a plasma reactor in which bias power of a single bias frequency only is coupled to the wafer from the ESC. This method is inaccurate when more than one bias frequency is present. For example, the reactor may apply bias power having a low frequency (LF) component and a high frequency (HF) component in order to obtain a favorable ion energy distribution for a plasma process such as plasma enhance reactive ion etching. A large error in wafer voltage measurement occurs when such a dual frequency bias is employed. We have found that the error in the wafer voltage measurement in such a case can create a clamping voltage error exceeding the capacity of the ESC's D.C. voltage supply.
What is needed is an accurate way of measuring wafer voltage with a dual frequency bias. This would permit the clamping voltage to be set to values closer either the maximum or minimum allowed clamping voltage without fear of violating these limits due to wafer voltage measurement errors. This in turn permits the wafer temperature range to be expanded accordingly, a significant advantage.